Keywords

Benchmark testing, Hardware, Field programmable gate arrays, Structural Comparison, Functional Equation, Mapping Algorithm, Physical Implementation, Input Signal, Encryption, Role In Design, Boolean Logic, Circuit Design, Open-source Tool, Comparison Tool, Commercial Tools, Digital Circuits, Synthesis Tool, Physical Transformation, Defense Applications, Reverse engineering, Logic gates, Benchmark testing, Hardware, Design Verification, Trojan horses, field programmable gate arrays, FPGA, Xilinx, Vivado, Project X-Ray, Fasm2bels, Bitstream Reversal, Structural Comparison, Implemented Design, hard-block primitives, hardware trojan detection, high-level circuit structures, low-level design analyses, multibit signals, VTR benchmarks, LEON Processor, Bitstream Validation

Abstract

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation information to perform a series of transformations on the netlist, which do not affect its functionality, but ensure it structurally matches what is physically implemented on the FPGA. Second, we present a structural mapping and equivalence checking algorithm that verifies this physical netlist exactly matches the bitstream. We validate this process on several benchmark designs, including checking for false positives by injecting hundreds of design modifications

Original Publication Citation

R. McKendrick, K. Faulkner and J. Goeders, "Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison," 2023 International Conference on Field Programmable Technology (ICFPT), Yokohama, Japan, 2023, pp. 142-151, doi: 10.1109/ICFPT59805.2023.00021.

Document Type

Conference Paper

Publication Date

2023-12-14

Publisher

IEEE

Language

English

College

Ira A. Fulton College of Engineering

Department

Electrical and Computer Engineering

University Standing at Time of Publication

Associate Professor

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