Keywords

Reverse engineering, Logic gates, Benchmark testing, Shift registers, Hardware, Behavioral sciences, Trojan horses, field programmable gate arrays, reverse engineering, 7-series Xilinx FPGA primitive platforms, block memories, carry chains, DANA, gate-level netlist reverse engineering, hard-block primitives, hardware trojan detection, high-level circuit structures, low-level design analyses, multibit signals, VTR benchmarks, word groupings, word reconstruction process tool

Abstract

While attempting to perform hardware trojan detection, or other low-level design analyses, it is often necessary to inspect and understand the gate-level netlist of an implemented hardware design. Unfortunately this process is challenging, as at the physical level, the design does not contain any hierarchy, net names, or word groupings. Previous work has shown how gate-level netlists can be analyzed to restore high-level circuit structures, including reconstructing multi-bit signals, which aids a user in understanding the behavior of the design. In this work we explore improvements to the word reconstruction process, specific to FPGA platforms. We demonstrate how hard-block primitives in a design (carry chains, block memories, multipliers) can be leveraged to better predict which signals belong to the same words in the original design. Our technique is evaluated using the VTR benchmarks, synthesized for a 7-series Xilinx FPGA, and the results are compared to DANA, a known word reconstruction tool.

Original Publication Citation

R. McKendrick, C. Simpson, B. Nelson and J. Goeders, "Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering," 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, 2022, pp. 1-5, doi: 10.1109/ICFPT56656.2022.9974401.

Document Type

Conference Paper

Publication Date

2022-12-15

Publisher

2022 International Conference on Field-Programmable Technology (ICFPT)

Language

English

College

Ira A. Fulton College of Engineering

Department

Electrical and Computer Engineering

University Standing at Time of Publication

Graduate Student

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