Keywords

FPGA, Glitch Reduction, Power

Abstract

Sponsorship: NASA Earth Science Technology Office (ESTO). While FPGAs provide exibility for performing high-performance DSP functions, they consume a significant amount of power. For arithmetic circuits, a large portion of the dynamic power is wasted on unproductive signal glitches. Pipelining can be used to significantly reduce the unproductive power wasted in signal glitches. This paper presents a methodology for estimating the amount of power consumed by glitches and applies this methodology to non-pipelined, pipelined, and digit-serial multipliers. This glitch estimation is used to evaluate these multipliers using four energy metrics: energy per operation, energy delay, energy throughput, and energy density. Understanding the energy cost of arithmetic operators can be used to aid the designer or synthesis tool in the creation of energy efficient datapath circuits.