Keywords

FPGA, SEU

Abstract

As process geometry sizes continue to decrease, microelectronics are becoming more vulnerable to the effects of radiation. Of particular concern are the effects of Single-Event Upsets (SEU) in Field Programmable Gate Arrays (FPGA). An SEU causes a dynamic memory element, such as a flip-flop or latch, to unwantedly change state. Since FPGAs are becoming an increasingly attractive solution for space system electronics, it is desirable to predict static on-orbit SEU rates likely to be encountered by a particular device for any particular orbit. Mean Time Between Failure (MTBF) can directly be calculated from a static SEU rate, allowing a system designer to estimate the overall reliablity of their system. Sponsorship: Los Alamos National Laboratory

Original Publication Citation

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