Keywords
FPGA Reliability, TMR
Abstract
Sponsorship: Los Alamos National Labs (LA-UR-03-7525). Field programmable gate arrays (FPGAs) are sensitive to radiation-induced single event upsets (SEUs) within the configuration memory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by SEUs. This paper evaluates the effectiveness and cost of TMR on two different counter designs in the presence of SEUs. The evaluation measures the reliability, area cost, and speed of different TMR styles. The tests show that when feedback TMR is used with triplicated clocks, it is possible to have counter design which is insensitive to any single configuration upset.
Original Publication Citation
13
BYU ScholarsArchive Citation
Graham, Paul S.; Rollins, Nathaniel; Wirthlin, Michael J.; and Caffrey, Michael P., "Evaluating TMR Techniques in the Presence of Single Event Upsets" (2003). Faculty Publications. 1048.
https://scholarsarchive.byu.edu/facpub/1048
Document Type
Peer-Reviewed Article
Publication Date
2003-09-11
Permanent URL
http://hdl.lib.byu.edu/1877/44
Publisher
NASA Office of Logic Design
Language
English
College
Ira A. Fulton College of Engineering and Technology
Department
Electrical and Computer Engineering
Copyright Status
© 2003 Los Alamos National Laboratory
Copyright Use Information
http://lib.byu.edu/about/copyright/