Abstract
Many avenues exist to insert malicious circuitry into an FPGA designs, including compromised CAD tools, overwriting bitstream files, and post-deployment attacks. The proprietary nature of the Xilinx bitstreams precludes the ability to validate an implemented design. This thesis introduces the BitRec and IPRec projects in an effort to support trojan detection tools. BitRec provides a novel approach to mapping of the Xilinx bitstream format into FPGA features in order to recreate the original design's netlist. BitRec supports the 7 Series, UltraScale and UltraScale+ architectures. IPRec then provides a novel approach to recognizing parameterizable IP within a flattened netlist in an effort to eliminate large sections of trusted circuitry from needing to be analyzed by a trojan detection tool.
Degree
MS
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
Rights
https://lib.byu.edu/about/copyright/
BYU ScholarsArchive Citation
Simpson, Corey Ryan, "Towards Trojan Detection from a Raw Bitstream" (2022). Theses and Dissertations. 9456.
https://scholarsarchive.byu.edu/etd/9456
Date Submitted
2022-03-23
Document Type
Thesis
Handle
http://hdl.lib.byu.edu/1877/etd12093
Keywords
FPGA, bitstream, Xilinx, trojan, IP
Language
english