Abstract

Commercial Off The Shelf (COTS) hardware has the advantages of low cost, modularity, and is easily upgraded. For Multiple-Input Multiple-Output (MIMO) space-time algorithms to be practical they must have the processing capability to execute in real-time. This makes COTS ideal for real-time MIMO research where the processing power increases exponentially with a linear increase in antennas. The BYU Electrical Engineering wireless lab has designed and built an eight processor transmitter and a twenty processor receiver to research and develop MIMO wireless communication. The Alamouti, 2 x 2 and 4 x 4 differential space-time MIMO algorithms have been partially implemented on the receiver using a variety of common parallel processing topologies to include: bus, line/ring, star, grid, hypercube, binary tree, and pyramid. Processor and inter-processor communication benchmarks were measured and used to quickly explore the performance of the previously mentioned topologies without expending time and effort on a full implementation of these MIMO algorithms using each topology. This methodology has the benefit of the creation of software libraries that can be used for testing or for complete MIMO algorithm implementation in the future. This thesis shows that a simple bus-based topology gives the best results when combined with the 4 x 4 differential space-time algorithm. This thesis also shows that if the number of receiving channels and processors increase at the same rate as the 2 x 2 to the 4 x 4 differential cases, then the ratio of decoding processing time to inter-processor communication time is reduced. If this trend continues, inter-processor communication will require more processing time than the actual space-time decoding algorithm. Due to the exponential increase in required processing, doubling the processing requirements obtained from the 4 x 4 case is not an adequate solution to implement real-time 8 x 8 differential decoding. As such, the BYU wireless lab's test system does not have enough processors to implement real-time 8 x 8 differential decoding. The BYU wireless lab should concentrate on a complete 4 x 4 implementation with increased bandwidth to make full use of the available processing power. The 8 x 8 case should also be explored but without the expectation of real-time communication. However, with the test system, additional DSP processors can easily be added to allow for increased processing requirements.

Degree

College and Department

Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering

Rights

http://lib.byu.edu/about/copyright/