Abstract

As the space industry expands, there is an increased reliance on system on chip (SoC) devices in high radiation environments. The reliability of these devices becomes crucial, especially in space applications. The industry's rapid growth has led to a massive expansion in the use of Commercial Off-The-Shelf (COTS) components. Electronic systems are vulnerable to single event upsets (SEUs) and the failure modes caused by SEUs are not fully understood, especially for COTS SoCs. Standard radiation testing techniques of SEUs use a single core of a multi-core processor to monitor bit flips. In this work, we present a parallelized radiation testing methodology that leverages the multiple cores of modern SoCs to test several components simultaneously. This approach allows limited beam time to be used more effectively and helps reveal different failure modes, as each part of the SoC is heavily interconnected. We implemented and evaluated this methodology across two neutron beam radiation tests at the ChipIr facility, testing the AMD Xilinx UltraScale+ MPSoC (Ultra96v2) and the Microchip's PolarFire SoC. Results demonstrate that the parallelized approach successfully characterizes per-component SEU cross sections for multiple components concurrently, and that the methodology is portable across devices with different architectures.

Degree

College and Department

Ira A. Fulton College of Engineering; Electrical and Computer Engineering

Rights

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