Abstract

Verilog to Routing (VTR) is the most widely used open-source tool for experimenting with FPGA placement and routing algorithms, as well as assessing how architectural changes impact routability, timing, and power consumption.

Historically, VTR has been tailored specifically for Intel’s Altera-like FPGAs, lacking support for key features that would enable greater flexibility in describing other architectures. In this work, we introduce a fully functional 7-Series architecture capture from the Xilinx family, utilizing VTR’s scalable architecture description language. We detail the necessary upgrades to achieve this description, including the ability to describe L and T-shaped wires and target hard multipliers with unequal input widths. Additionally, we explore various aspects of the 7-Series architecture and provide explanations for its design decisions.

Degree

College and Department

Ira A. Fulton College of Engineering; Electrical and Computer Engineering

Rights

https://lib.byu.edu/about/copyright/