Abstract

Within an ever-evolving radio-frequency (RF) environment, designers are required to adapt systems to increasingly constricted parameters. The available tools continually grow to match this need, but so does the complexity in using them. The radio-frequency system-on-chip (RFSoC) is an innovation that combines a field-programmable gate array (FPGA) with an integrated RF chain. Designing with an RFSoC allows for high-precision data transmission, sampling, and processing, but it can be difficult and time-consuming to develop specialized circuits. The open-source CASPER project aims to provide a library of abstracted block-design components to simplify the design process. An arbitrary waveform generator (AWG) is created with CASPER to allow for complicated waveform transmission or the capture and analysis of over-the-air signals. CASPER uses a mixed-mode clock manager (MMCM) to generate the clock that drives the RF data converter (RFDC) in RFSoCs. The dynamic reconfiguration port (DRP) on the MMCM is utilized to reconfigure the clock at runtime for additional flexibility in both transmit and receive. This DRP access is then implemented in the CASPER framework for repeatable and simple use across a variety of designs.

Degree

College and Department

Ira A. Fulton College of Engineering; Electrical and Computer Engineering

Rights

https://lib.byu.edu/about/copyright/