Keywords
netlist reverse engineering, graph neural networks, fpga, ip protection, design assurance
Abstract
Netlist reverse engineering enables many applications, including detecting IP theft, verifying CAD tool correctness, and detecting hardware trojans. However, reconstructing high-level information and circuit structure from a flat, nameless netlist is challenging. In this work we focus on the problem of locating known IP cores in an FPGA netlist, which is especially challenging due to the prevalence of highly configurable IP cores. We present Neurocore: a graph neural network-based approach to classifying nodes in a netlist as instances of known IP cores, and present and evaluate different models for different use cases. We have created a large open-source dataset of thousands of FPGA designs with known IP cores, and demonstrate that our approach can obtain 80–98% accuracy, depending on the model and the use case.
BYU ScholarsArchive Citation
Dahl, Dallin; Faulkner, Keenan; Usevitch, James; and Goeders, Jeffrey, "Neurocore: A GNN Approach to Configurable IP Core Identification in FPGA Netlists" (2026). Student Works. 439.
https://scholarsarchive.byu.edu/studentpub/439
Document Type
Peer-Reviewed Article
Publication Date
2026-02-03
Language
English
Link to Data Set(s)
https://github.com/byuccl/neurocore_fpt_2025
College
Ira A. Fulton College of Engineering
Department
Electrical and Computer Engineering
Copyright Status
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