FPGA Reliability, I/O
Sponsorship: Los Alamos National Laboratories (LA-UR-02-3163). Field programmable gate arrays (FPGAs) are an attractive alternative for space-based remote sensing applications. However, SRAM-based FPGAs are sensitive to radiation induced single-event upsets within the configuration memory. Such configuration upsets may change the logic, routing, and operating modes of a user FPGA design. Upsets within the configuration of an I/O block are especially troublesome as they may impact the operation of other system components. This paper will evaluate the operation of the I/O block within the Xilinx Virtex FPGA in the presence of configuration memory upsets and introduce techniques for detecting and repairing such failures.
Original Publication Citation
Nathan Rollins, Michael J. Wirthlin, Michael Caffrey, and Paul Graham, "Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets", 5th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Paper C3, September 22
BYU ScholarsArchive Citation
Graham, Paul S.; Rollins, Nathaniel; Wirthlin, Michael J.; and Caffrey, Michael P., "Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets" (2002). All Faculty Publications. 1068.
NASA Office of Logic Design
Ira A. Fulton College of Engineering and Technology
Electrical and Computer Engineering
© 2002 Los Alamos National Laboratory
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