Abstract

A method for measuring system-on-a-chip (SoC) cache upsets is presented and evaluated. In contrast to methods that predict cache contents through analysis or memory access patterns, this method uses system registers to read cache memories directly, thereby creating and checking golden copies to detect individual memory upsets during operation. The test method is driven by the device under test itself and does not require a user to set or know a priori the cache contents. A bare-metal implementation of this “direct golden method” on a Zynq UltraScale+ MPSoC logged upsets in the device’s data cache, data tag, and TLB RAM memories during a neutron radiation beam test. For each of these memories, this direct golden method yields cache upset bit cross sections, such as 7.115 × 10^−16 cm^2 for the data cache. Confidence intervals for these bit cross sections overlap such intervals for three other methods, supporting this method’s validity and candidacy for future use.

Degree

MS

College and Department

Electrical and Computer Engineering

Rights

https://lib.byu.edu/about/copyright/

Date Submitted

2022-06-02

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd12358

Keywords

cache, single event upset, memory upset, MPSoC, test method, neutron radiation, fluence, cross section, beam test

Language

english

Included in

Engineering Commons

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