Abstract

SpyDrNet is an open-source structural netlist representation framework written in Python that allows users to create, analyze, and manipulate structural netlists. The internal format was designed to hold generic source structural netlists. Verilog and EDIF netlists generated by Vivado were read and written by SpyDrNet. Additional API functionality was built around the netlist representation. An application applying triple modular redundancy and duplication with compare was created and successfully used.

Degree

MS

College and Department

Electrical and Computer Engineering

Rights

https://lib.byu.edu/about/copyright/

Date Submitted

2022-03-31

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd12083

Keywords

netlists, EDIF, Verilog, SpyDrNet, computer aided design, automation, digital circuits, circuit representations

Language

english

Included in

Engineering Commons

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