SpyDrNet is an open-source structural netlist representation framework written in Python that allows users to create, analyze, and manipulate structural netlists. The internal format was designed to hold generic source structural netlists. Verilog and EDIF netlists generated by Vivado were read and written by SpyDrNet. Additional API functionality was built around the netlist representation. An application applying triple modular redundancy and duplication with compare was created and successfully used.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Skouson, Dallin Mark, "SpyDrNet - An Open-Source Python Netlist Representation for Analysis and Transformation" (2022). Theses and Dissertations. 9446.
netlists, EDIF, Verilog, SpyDrNet, computer aided design, automation, digital circuits, circuit representations