Partial circuit replication is a soft error mitigation technique that uses redundant copies of a circuit to mask or detect the effects of soft errors. By masking or detecting the effect of soft errors on SRAM-based FPGAs, implemented circuits can be made more reliable. The technique is applied selectively, to only a portion of the components within a circuit. Partial application lowers the cost of implementation. The objective of partial circuit replication is to provide maximal benefit at limited or minimized cost. The greatest challenge of partial circuit replication is selecting which components within a circuit to replicate. This dissertation advances the state of the art in the effective use of partial circuit replication for masking and detecting soft errors in SRAM-based FPGAs. It provides a theoretical foundation in which the expected benefits and challenges of partial circuit replication can be understood. It proposes several new selection approaches for identifying the most beneficial areas of a circuit to replicate. These approaches are applied to two complex FPGA-based computer networking systems and another FPGA design. The effectiveness of the selection approaches are evaluated through fault injection and accelerated radiation testing. More benefit than expected is obtained through partial circuit replication when applied to critical components and sub-regions of the designs. In one example, in an open-source computer networking design, partial circuit replication masks and detects approximately 70% of failures while replicating only 5% of circuit components, a benefit-cost ratio of 14.0.
College and Department
Electrical and Computer Engineering
BYU ScholarsArchive Citation
Keller, Andrew Mark, "Partial Circuit Replication for Masking and Detecting Soft Errors in SRAM-Based FPGAs" (2021). Theses and Dissertations. 9326.
triple modular redundancy, duplication with compare, selective, radiation, SEU, mitigation