In this work a new technique for accelerating the aging of FPGA devices is proposed and demonstrated. The proposed technique uses harmful configurations (short circuits) to accelerate the aging process on targeted portions of an FPGA chip. A testbed is developed for the purpose of measuring FPGA degradation. Using this testbed it is shown that implementing thousands of short circuits in FPGA fabric generates enough heat to cause significant damage to the chip, reducing switching speeds by up to 8%. It is also demonstrated that different parts of the FPGA fabric can be aged at different rates, with some parts of the chip only slowing down 2% while other parts slowdown as much as 8%.
College and Department
Ira A. Fulton College of Engineering and Technology
BYU ScholarsArchive Citation
Gaskin, Tanner, "Exploring the Performance Impacts of Harmful FPGA Configurations" (2021). Theses and Dissertations. 9006.
fpga, cmos aging, security