Abstract

In this work a new technique for accelerating the aging of FPGA devices is proposed and demonstrated. The proposed technique uses harmful configurations (short circuits) to accelerate the aging process on targeted portions of an FPGA chip. A testbed is developed for the purpose of measuring FPGA degradation. Using this testbed it is shown that implementing thousands of short circuits in FPGA fabric generates enough heat to cause significant damage to the chip, reducing switching speeds by up to 8%. It is also demonstrated that different parts of the FPGA fabric can be aged at different rates, with some parts of the chip only slowing down 2% while other parts slowdown as much as 8%.

Degree

MS

College and Department

Ira A. Fulton College of Engineering and Technology

Rights

https://lib.byu.edu/about/copyright/

Date Submitted

2021-05-17

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd11645

Keywords

fpga, cmos aging, security

Language

english

Included in

Engineering Commons

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