As an extension of previous work done by Luke Newmeyer in his master's thesis \cite{newmeyer2018efficient}, this report presents an improved signal processing chain for efficient, real-time processing of radar data for small-scale UAV traffic control systems. The HDL design described is for a 16-channel, 2-dimensional phased array feed processing chain and includes mean subtraction, windowing, FIR filtering, decimation, spectral estimation via FFT, cross-correlation, and averaging, as well as a significant amount of control and configuration logic. The design runs near the the max allowable memory bus frequency at 300MHz, and using AXI DMA engines can achieve throughput of 38.3 Gb/s (~0.25% below theoretical 38.4 Gb/s), transferring 2MB of correlation data in about 440us. This allows for a pulse repetition frequency of nearly 2kHz, in contrast to 454Hz from the previous design. The design targets the Avnet UltraZed-EV MPSoC board, which boots custom PetaLinux images. API code and post-processing algorithms run in this environment to interface with the FPGA control registers and further process frames of data. Primary configuration options include variable sample rate, window coefficients, FIR filter coefficients, chirp length, pulse repetition interval, decimation factor, number of averaged frames, error monitoring, three DMA sampling points, and DMA ring buffer transfers. The result is a dynamic, high-speed, small-scale design which can process 16 parallel channels of data in real time for 3-dimensional detection of local UAV traffic at a range of 1000m.



College and Department

Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering



Date Submitted


Document Type





FPGA-Accelerated Digital Signal Processing for UAV Traffic Control Radar



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Engineering Commons