Abstract

The StrongARM comparator is utilized in many analog-to-digital converters (ADCs) because of its high power efficiency and rail-to-rail outputs. The performance of the comparator directly affects the speed, power, and accuracy of an ADC. However, the StrongARM comparator performance parameters such as delay, noise, and offset measured directly from silicon prototypes are rare in literature and often consist of small sample sets. In addition, existing techniques to measure the comparator require large chip areas, making it impractical to characterize a large number of comparators to obtain stochastic parameters such as offset and noise. This work presents novel circuit techniques to measure a large number of comparators (4,000) in a compact chip area to directly obtain silicon data including delay, noise, offset, and power. The proposed techniques also relax the requirement on the test instruments to measure the small time values. Four comparators with different transistor size ratios have been designed and measured to study the performance tradeoffs. In addition, this work presents a method utilizing supercomputing resources to simulate the large design space of the StrongARM comparator to observe the performance trends. Measurements are compared to simulations showing their accuracy and, for the first time, detailed study on the performance trends with different transistor size ratios.

Degree

MS

College and Department

Ira A. Fulton College of Engineering and Technology

Rights

https://lib.byu.edu/about/copyright/

Date Submitted

2019-10-29

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd11459

Keywords

StrongARM, comparator, latch, input-referred noise, delay, energy, supercomputer cadence simulations

Language

English

Included in

Engineering Commons

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