Abstract

For applications such as live video processing, there is a high demand for high performance and low latency solutions. The configurable logic in FPGAs allows for custom hardware to be tailored to a specific video application. These FPGA designs require technical expertise and lengthy implementation times by vendor tools for each unique solution. This thesis presents a dynamically configurable topology as an FPGA overlay to deploy custom hardware processing pipelines during run-time by utilizing dynamic partial reconfiguration. Within the FPGA overlay, a configurable topology with a routable switch allows video streams to be copied and mixed to create complex data paths. This work demonstrates a dynamic video processing pipeline with 11 reconfigurable regions and 16 unique processing cores, allowing for billions of custom run-time configurations.

Degree

MS

College and Department

Ira A. Fulton College of Engineering and Technology

Rights

https://lib.byu.edu/about/copyright/

Date Submitted

2020-06-23

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd11367

Keywords

Xilinx, FPGA, dynamic partial reconfiguration, high-level synthesis, video processing

Language

english

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