Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the circuit's netlist and how the circuit is placed and routed on the FPGA. TMR with repair showed a neutron cross-section improvement of 100x while the best mitigation technique proposed in this work showed an improvement of 700x.This work demonstrates both some causes behind single bit SEU failures for TMR circuits on FPGAs and mitigation techniques to address these failures. In addition to these findings, this work also shows that the majority of radiation failures in these circuits are caused by multiple cell upsets, laying the path for future work to further enhance the effectiveness of TMR on FPGAs.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Cannon, Matthew Joel, "Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing" (2019). Theses and Dissertations. 7551.
FPGA, reliability, SEE, SEU, radiation effects, TMR, MTTF, fault injection, radiation testing, Markov chain, single bit failure, single point failure, common mode failure, common cause failure, CAD, incremental placement, incremental routing