Feature detection, description and matching are crucial steps in many computer vision algorithms. These rely on feature descriptors to be able to match image features across sets of images. This paper discusses a hardware implementation and various optimizations of our lab's previous work on the SYnthetic BAsis feature descriptor (SYBA). Previous work has shown that SYBA can offer superior performance to other binary descriptors, such as BRIEF. This hardware implementation on an FPGA is a high throughput and low latency solution, which is critical for applications such as: high speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. Finally, we compare our solution to other hardware methods. We believe that our implementation of SYBA as a feature descriptor in hardware offers superior image feature matching performance and uses less resources than most binary feature descriptor implementations.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Fuller, Samuel Gaylin, "Optimization and Hardware Implementation of SYBA-An Efficient Feature Descriptor" (2019). Theses and Dissertations. 7520.
SYBA, FPGA, Feature, Descriptor, Binary