Abstract

The rapid increase in the density of modern FPGAs has allowed ever increasingly complex designs to be mapped to FPGAs. However, this increase in logic resources is accompanied by an increase in the complexity of describing and verifying the operation of an application. This has prompted the search for new approaches to the design, debug and verification of circuits. The desire to find more effecient approaches to designing these large FPGA circuits has led to the creation of synthesizing compilers that can create hardware from high-level descriptions based on general purpose programming languages. Being able to describe the application at a high level of abstraction allows the designer to focus on the algorithms, rather than the implementation details. Though synthesizing compilers can make it easier to create circuits, they can make it more difficult to debug the resulting circuit. Typically, a design is debugged and verified by simulating the application/circuit in software (possibly at many different levels of abstraction). However, because of the reprogrammability of FPGAs, it is possible to use the FPGA device directly during the debug process. Performing design debug verification in the FPGA device has two significant advantages. First, the debugging occurs in the hardware itself and not a virtual abstraction. Second, debugging in hardware occurs at hardware speeds, which is orders of magnitude faster than software simulation. These two advantages make it possible to continue to verify large FPGA based designs.

Degree

PhD

College and Department

Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering

Rights

http://lib.byu.edu/about/copyright/

Date Submitted

2004-04-01

Document Type

Dissertation

Handle

http://hdl.lib.byu.edu/1877/etd405

Keywords

FPGA, source level debugging, synthesis

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