Abstract

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This work introduces and contrasts seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks is reported. The work demonstrates that one of the algorithms provides the best overall timing performance results with an average 8.5% increase in critical path length over a triplicated design without voters and a 29.6% area increase. Another algorithm provides far better area results (an average 3.4% area increase over a triplicated design without voters) at a slightly higher timing cost (an average 14.9% increase in critical path length over a triplicated design without voters). In addition, this work demonstrates that restricting synchronization voter locations to flip-flop output nets is an effective heuristic for minimizing the timing performance impact of synchronization voter insertion.

Degree

College and Department

Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering

Rights

http://lib.byu.edu/about/copyright/