adaptive self-organizing concurrent system, PASOCS, multi-chip module, neural network learning
This paper presents a VLSI implementation of the Priority Adaptive Self-organizing Concurrent System (PASOCS) learning model that is built using a multi-chip module (MCM) substrate. Many current hardware implementations of neural network learning models are direct implementations of classical neural network structures - a large number of sample computing nodes connected by a dense number of weighted links. PASOCS is one of a class of ASOCS (Adaptive Self-Organizing Concurrent System) connectionist models whose overall goal is the same as classical neural networks models, but whose functional mechanisms differ significantly. This model has potential application in areas such as pattern recognition, robotics, logical inference, and dynamic control.
Original Publication Citation
Stout, M., Rudolph, G., Martinez, T. R., and Salmon, L., "A VLSI Implementation of a Parallel Self-Organizing Learning Model", Proceedings of the 12th International Conference on Pattern Recognition, vol. 3, pp. 373-376, 1994.
BYU ScholarsArchive Citation
Martinez, Tony R.; Rudolph, George L.; Salmon, Linton G.; and Stout, Matthew G., "A VLSI Implementation of a Parallel, Self-Organizing Learning Model" (1994). All Faculty Publications. 1167.
Physical and Mathematical Sciences
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