Intellectual Property (IP) is used to speed up the design process and save money. The use of IP and complex CAD tools reduce visibility into the design and what is actually happening during synthesis and implementation. All of the complexity makes it easier for an attacker to insert malicious logic or tamper with the design in ways that are difficult to detect. Not very much work has been done towards the creation of tools to facilitate the safe use of 3rd-party IP. This work presents Physical and Functional Assurance, two approaches that aim to accomplish this task through physically and logically identical IP instantiation respectively. The approaches and their results and performance impact are presented across a suite of 53 experiments. The Physical Assurance approach is successful at instantiating the 3rd-party IP in the user design without modification and it is also successful at catching even minute tampers along the way. The Functional Assurance approach is shown to be feasible, but still requires work to become a fully-fledged tool.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Jensen, Sean Talbot, "Towards Tools for Achieving Third-Party IP Assurance" (2018). Theses and Dissertations. 6691.
trust, FPGA, intellectual property, Physical Assurance, Functional Assurance, 3rd-party IP, trusted vendor