Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents a generic bootstrap framework that can be used to construct a variety of bootstrap designs. This thesis also discusses necessary PR design rules and techniques for bootstrap design creation. Additionally, this thesis presents two applications that demonstrate the feasibility of bootstrapping. One application is a bootstrap loader featuring a PCI Express endpoint; this loader is capable of reconfiguring a subset of the hardware on an as-need basis. The other application is a prototype designed to demonstrate the bootstrapping for nonvolatile configuration memory reduction in space-bound payloads. While bootstrap design is more complex than standard FPGA designs, bootstrapping increases the flexibility and capability of FPGAs.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Ostler, Patrick Sutton, "FPGA Bootstrapping Using Partial Reconfiguration" (2011). All Theses and Dissertations. 2878.
FPGA, partial reconfiguration, bootstrapping, PCI Express