When designing custom hardware to implement signal processing algorithms, it is important to select bitwidths that meet the minimum error requirements while minimizing implementation area. Larger bitwidths reduce error, but increase area, while selecting smaller bitwidths does the opposite. Finding the set of bitwidths that produces the smallest area that still meets the error requirements has been shown to be NP-hard. To address this problem, many heuristics have been developed. Unfortunately, they are not always well documented and do not have available source code. It is also di cult to know which algorithm to try to use. This thesis addresses these challenges in several ways. It provides the necessary background information to understand bitwidth optimization algorithms, as well as a survey of the existing literature. It also presents a new framework called Bitwidth Analysis Tool (BAT) built on the open source Ptolemy tool. This framework is designed to help implement and compare bitwidth optimization algorithms. Some existing algorithms are implemented within this new framework, and compared with each other on a variety of benchmarks. The comparison results verify that because the tested algorithms are heuristics, no single algorithm gives the best results in all cases. It is therefore important to test a variety of algorithms to try to find the best answer. The results also show existing algorithms and error models provide a good starting point, but existing error models do not yet provide sufficiently tight bounds to be useful in large complex systems.



College and Department

Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering



Date Submitted


Document Type





FPGA, xed-point, bitwidth analysis, digital signal processing, DSP, Ptolemy