This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Bartholomew, David Ray, "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit" (2004). All Theses and Dissertations. 126.
design, high speed, mixed-signal, CMOS, mutliplier, circuit, circuit design, short-channel, PMOS, transistors, MOSFET, Cadence Design Systems, nonlinearity, filtering, digital to analog conversion, linear equalization, short-channel effects