Abstract

Field-Programmable Gate Arrays (FPGAs) leveraging soft processors, particularly those implementing the open-standard RISC-V Instruction Set Architecture (ISA), are increasingly important for space missions due to their adaptability and reconfigurability. However, their susceptibility to radiation-induced Single Event Upsets (SEUs) presents significant reliability challenges, necessitating robust fault-tolerant strategies such as Triple Modular Redundancy (TMR). This dissertation evaluates the effectiveness of TMR-based mitigation techniques for Linux-capable soft RISC-V System-on-Chip (SoC) implementations deployed on SRAM-based FPGAs operating in high-radiation environments. Using a combination of deterministic fault injection and neutron radiation testing, this work identifies critical residual single-point failure modes that persist in TMR-protected designs. To address these vulnerabilities, additional mitigation strategies are proposed and validated, including SEU-aware placement constraints and error-correcting techniques applied to memory subsystems. Experimental results demonstrate significant reliability improvements, achieving up to a 20x— increase in Mean Time Between Failures (MTBF) and an estimated 95% failure coverage with the use of additional analysis-driven mitigation. The key contributions of this work include: (1) a structured fault analysis methodology that traces SEUs to system-level failure modes, (2) validated design enhancements that improve fault tolerance with minimal resource overhead, and (3) radiation-backed experimental data across multiple soft SoC platforms. Together, these results provide a practical framework for designing resilient, high-reliability FPGA-based systems suitable for next-generation space and mission-critical applications.

Degree

PhD

College and Department

Ira A. Fulton College of Engineering; Electrical and Computer Engineering

Rights

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