Keywords

fpga, reverse engineering, netlist

Abstract

Netlist reverse engineering has many uses, from detecting hardware trojans to recovering missing design source files. However, the basic problem of finding IP in a netlist has not been widely discussed. The problem boils down to subgraph isomorphism on graphs constructed from netlists. We present two approaches to identifying IP in larger circuits. IPRec focuses on exploiting hierarchy in the IP design and is a rather conservative approach, while Isoblaze focuses on local properties and connectivity and is more liberal in matching.

Document Type

Peer-Reviewed Article

Publication Date

2023-11-20

Language

English

College

Ira A. Fulton College of Engineering and Technology

Department

Electrical and Computer Engineering

University Standing at Time of Publication

Graduate Student

Share

COinS