FPGA Power, TMR
Sponsorship: Los Alamos National Laboratory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by single event upsets (SEUs). The SEU immunity that TMR provides comes at the cost of increased design area and decreased speed. Additionally, the cost of increased power due to TMR must be considered. This paper evaluates the power costs of TMR and validates the evaluations with actual measurements. Sensitivity to design placement is another important part of this study. Power consumption costs due to TMR are also evaluated in different FPGA architectures. This study shows that power consumption rises in the range of 3x to 7x when TMR is applied to a design.
Original Publication Citation
Nathan Rollins, Michael J. Wirthlin, and Paul Graham, Evaluation of Power Costs in Applying TMR to FPGA Designs, 7th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Paper 136, September 24
BYU ScholarsArchive Citation
Rollins, Nathaniel; Wirthlin, Michael J.; and Graham, Paul S., "Evaluation of Power Costs in Applying TMR to FPGA Designs" (2004). All Faculty Publications. 419.
NASA Office of Logic Design
Ira A. Fulton College of Engineering and Technology
Electrical and Computer Engineering
© 2004 Nathaniel Rollins, Michael J. Wirthlin, and Paul S. Graham
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