Reducing Energy in FPGA Multipliers Through Glitch Reduction - Clock Power and Digit-Serial Addendum
Keywords
energy, FGPA multipliers, glitch reduction
Abstract
Sponsorship: NASA. In a previous paper it was shown that reducing the amount of glitches in digital designs can significantly reduce the amount of dynamic power consumption. Pipelined multipliers and a bit-serial multiplier design were used to show this. The paper failed to mention how much of the dynamic power consumption was due to the clock distribution. Also the only digit- serial multiplier digit size investigated was a digit size of 1. This paper addresses the issue of dynamic clocking power and includes results of digit-serial multipliers with larger digit sizes.
BYU ScholarsArchive Citation
Rollins, Nathaniel and Wirthlin, Michael J., "Reducing Energy in FPGA Multipliers Through Glitch Reduction - Clock Power and Digit-Serial Addendum" (2006). Faculty Publications. 1322.
https://scholarsarchive.byu.edu/facpub/1322
Document Type
Report
Publication Date
2006-01-01
Permanent URL
http://hdl.lib.byu.edu/1877/71
Language
English
College
Ira A. Fulton College of Engineering and Technology
Department
Electrical and Computer Engineering
Copyright Status
© 2006 Nathaniel Rollins and Michael J. Wirthlin
Copyright Use Information
http://lib.byu.edu/about/copyright/