level-oriented model, timed asynchronous circuits, formal verification, time Petri nets
Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification.
Original Publication Citation
T. Kitai, Y. Oguro, T. Yoneda, E. G. Mercer, and C. J. Myers, "Level-oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method," in Proceedings of Pacific Rim International Symposium on Dependable Computing, pages 21-22, 22.
BYU ScholarsArchive Citation
Mercer, Eric G.; Kitai, Tomoya; Myers, Chris; Oguro, Yusuke; and Yoneda, Tomohiro, "Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method" (2002). All Faculty Publications. 1069.
Physical and Mathematical Sciences
© 2002 Institute of Electrical and Electronics Engineers
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