Abstract

This work is an analysis of solutions to problems derived from inherent timing and signal integrity issues in the use and application of the IEEE 1149.1 Standard at the board level in conjunction with its test system. Setup or hold times violations may occur in a boundary scan chain using IEEE 1149.1 compliant devices. A practical study of the TDI-TDO scan data path has been conducted to show where problems may arise in relationship to a particular board topology and test system. This work points to differences between passing and failing scan path tests for problem characterization. Serial data flow is then analyzed and suitability is discussed. Within certain conditions, a solution is proposed. This work has been shown to work on the test system. Recommendations are made based on this experimental approach.

Degree

MS

College and Department

Ira A. Fulton College of Engineering and Technology; Technology

Rights

http://lib.byu.edu/about/copyright/

Date Submitted

2004-11-04

Document Type

Thesis

Handle

http://hdl.lib.byu.edu/1877/etd587

Keywords

1149.1, signal integrity, tck, boundary scan, layout, printed circuit test

Technology Emphasis

Information Technology (IT)

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