This work deals with evaluating the effectiveness of a new verification algorithm called slice--n--dice. In order to evaluate the effectiveness of slice--n--dice, a vector clock POR was implemented to compare it against. The first paper contained in this work was published in ACM SIGSOFT Software Engineering Notes and discusses the implementation of the vector clock POR. The results of this paper show the vector clock POR performing better than the POR in Java Pathfinder by at least a factor of two. The second paper discusses the implementation of slice--n--dice and compares it against other verification techniques. The results show that slice--n--dice performs better than the other verification methods in terms of states explored and runtime when there is no error in the program or little thread interaction is needed in order for the error to manifest.
College and Department
Physical and Mathematical Sciences; Computer Science
BYU ScholarsArchive Citation
Noonan, Eric S., "Slice—n—Dice Algorithm Implementation in JPF" (2014). All Theses and Dissertations. 4147.
state explosion, partial order reduction, slicing and dicing