This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory scrubbing. Regional SEU rates and the change in CFE's SEU rate over time show the measurable, expected effects of the South Atlantic Anomaly and the cycle of solar activity on CFE's SEU rates. The results of the on-orbit experiments developed for this work demonstrate that FPGA devices can be used to provide reliable, high-performance processing to space applications when proper SEU mitigation strategies are applied to the designs implemented on the FPGAs.
College and Department
Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering
BYU ScholarsArchive Citation
Howes, William A., "On-Orbit FPGA SEU Mitigation and Measurement Experiments on the Cibola Flight Experiment Satellite" (2011). All Theses and Dissertations. 2474.
FPGA, SDRAM, reliability, space-based computing, SEU mitigation, SEU rate prediction and measurement